The development of dynamic random access memories (DRAMs) has made possible the storage capability of over four million bits in a single integrated circuit chip. The packing density of the cells of such memories has been optimized by reducing the area of components comprising each cell. Typically, MOS DRAM cells include a single transistor and a single capacitor for storing the electrical charge corresponding to a logic high or low level. With such a construction, each cell of the memory array is required to be periodically refreshed so as to maintain the logic level stored on the cell capacitor.
MOS memory arrays can be made smaller in size by scaling the entire array, i.e., reducing the size of each component or feature of the array. This, however, has reached a limiting point, in that with small storage capacitors the charge storage capability is reduced, and thus the electrical signal output therefrom becomes difficult to distinguish from noise and other electrical intereference normally found in the array. Hence, complex sense amplifiers are required to distinguish the readout signal from the noise signals.
In view of the inherent limitations which accompany the one-transistor DRAM cell, a new type of DRAM cell, with dynamic gain, has been proposed. The construction and operation of one such DRAM cell is disclosed in a technical article "TITE RAM` a New SOI DRAM Gain Cell For Mbit DRAM's", 16th International Conference on Solid State Devices and Materials, 1984, pp. 265-268, S. Banerjee et al. Disclosed in the article is a planar two-transistor DRAM cell employing a pass transistor during write operations to couple charge from a write bit line to the small area storage capacitor. The word line capacitance associated with the cell is capacitively coupled to the storage capacitor, thereby forming a capacitor divider. When the word line is driven during read operations of the cell, the voltage on the storage, node is boosted to a voltage depending on the charge previously stored thereon. The capacitor forms a part of a gain transistor which is adapted to connect a voltage source to a read bit line. If little or no charge is stored on the capacitor, the boosted voltage on the storage node is insufficient to turn on the gain transistor strongly, whereby a precharged voltage existing on the read bit line is not disturbed significantly. However, if a substantial charge has been previously stored on the storage capacitor, the boosted voltage during read operations is sufficient to drive the gain transistor into conduction, thereby placing a substantial charge on the read bit line.
While the two-transistor DRAM cell provides an internal readout gain not found in the one-transistor cell, several shortcomings are still inherent with the cell. First, with small-area planar cells, the storage capacitor is also limited to a small size. Secondly, because the series capacitances of the word line and cell capacitor are usually constructed in different process steps, such capacitances cannot be carefully controlled and thus the magnitude of the boosted voltage applied to the gain transistor also cannot be carefully defined. In addition, the pass transistor of such a two-transistor DRAM cell is most efficiently fabricated using polycrystalline silicon (polysilicon). Such type of transistor is inherently leaky, and thus needs to be refreshed more frequently.
From the foregoing, it can seen that a need exists for an improved gain-type DRAM cell in which the capacitance of the storage capacitor can be made large without significantly affecting the area required by the cell. An associated need exists for a gain-type DRAM cell which can be constructed with a high quality pass transistor to thereby improve the performance of such a cell.